Home > Second Generation Double-Data-Rate (DDR2) Digital Controller and PHY Second Generation Double-Data-Rate (DDR2) Digital Controller and PHY Project TitleSecond Generation Double-Data-Rate (DDR2) Digital Controller and PHY Project ReferenceARD/045 Project Type Project Period20081231 - 20090630 Funds Approved (HK$’000)1960 Project CoordinatorDr Shen-chang Chao Deputy Project Coordinator Deliverable Research Group Sponsor Description Co-Applicant
