High Speed & Agile Direct Digital Synthesizer
20121021 - 20150120
Dr Beiping Yan
1) 1 GSPS (Sampling per second) DDS without internal clock (phase locked loop or PLL). All key blocks, including 32-bit DDS core, 12 bit high speed DAC, and efficient I/O interface, will be designed and verified based on CSMC 130 nm CMOS technology. 1 GSPS DDS samples without PLL will be delivered within the first 6 months. 2) 1 GSPS DDS with internal clock. A PLL circuit will be added in the above-mentioned 1GSPS DDS to facilitate the applications for clock source and siganl generation. 1 GSPS DDS IPs and samples with PLL will be delivered within 12 months. 1 GSPS DDS IPs include 1) 32-bit DDS core, 2) 12-bit high speed DAC, 3) efficient I/O and ESD interface, and 4) integrated 1 GSPS DDS. 3) 2 GSPS DDS without internal clock. All key blocks, including 32-bit DDS core, 12 bit high speed DAC, and high speed interface, will be designed and verified based on SMIC 65 nm technology. 2 GSPS DDS samples without PLL will be delivered within 15 months. 4) 2 GSPS DDS with internal clock. A PLL circuit will be added in the above-mentioned 2 GSPS DDS to facilitate the applications for clock source and siganl generation. 2 GSPS DDS IP and samples with PLL will be delivered within 21 months. 2 GSPS DDS IPs include 1) 32-bit DDS core, 2) 12-bit high speed DAC, 3) efficient I/O & ESD interface, and 4) integrated 2 GSPS DDS.
Dr Keh-chung Wang Mr David Kwong Dr Xiao Huo Dr Zhongzi Chen Dr Xiaowu Cai Miss Sidar Lai Mr Norman FOK Mr Chenxi Wei Mr Tao Sun Miss Nan Guo Mr Leung Ling Alan Pun Mr Gangjie Jacky Cai Mr Tat Fu Chan Mr Zuqiang Tang Mr Sze Wing, Brian Leung Mr Zhuqing Joe Feng
CSMC Technologies [Sponsor] CSMC Technologies Fab 1 Company Limited (Licensing Income) [Sponsor] Institue of Microelectronics of CAS RCL Semiconductor Ltd RCL Semiconductor Ltd (contract service) SMIC [Sponsor] SMIC (licensing) [Sponsor]
Software defined radio （SDR） will be one of the major trends of next generation wireless communication. The idea of the SDR is to use software programming to realize all communication modes with different standards and protocols in a single transceiver platform. Because of the digitally programming requirement, the direct digital frequency synthesizer (DDS) becomes a key component of the SDR hardware platform. The goal of this project is to design and verify a high speed and agile DDS chip using ASTRI’s algorithm and architecture, and license IP to IC industry. All designs will be carried out using EDA tools. The function blocks of the DDS will be built using specific foundry's device models. After the schematic and simulation is completed, the layout design will be implemented. Then a post-simulation will be done to confirm the circuit function. The tape-out of a test chip will be completed after DRC/LVS check. The real functions of the DDS will be tested and verified on the test chip. DDS is an emerging technology compared to the traditional frequency synthesizer. It can also be used in many other fields besides the SDR application, such as automatic testing equipment (ATE), medical imaging, cable modem, and phased array systems. DDS will permeate to every corner of our daily life in the future.