“Our intent is to provide a long-lived open ISA with significant infrastructure support, including documentation, compiler tool chains, operating system ports, reference software simulators, cycle-accurate FPGA emulators, high-performance FPGA computers, efficient ASIC implementations of various target platform designs, configurable processor generators, architecture test suites, and teaching materials. Initial versions of all of these have been developed or are under active development. This material is to be made available under open-source licenses.” …K Asanovic
In this seminar, Professor Krste Asanovic and Yunsup Lee of University of California Berkeley will share with us their vision, explain the underlying advantages of RISC-V, and illustrate with an example of RISC-V based SOC designs they did at Berkeley which may out-perform the industry leaders in embedded processor IP.
|Venue||Conference Hall 4-7, 2/F Lakeside 2, Phase II, Hong Kong Science Park, Shatin N.T|