Senior Engineer/ Engineer, ASIC Design

Senior Engineer/ Engineer, ASIC Design

Job Description


Job Responsibilities

  • Assist in R&D project development.
  • Carry out logic design, module-level or top-level verification.
  • Carry out firmware design to support ASIC development.
  • Research in latest Digital Communications or Cryptography and applications.


  • Bachelor’s Degree in Computer Engineering/ Electronic Engineering/ Electrical Engineering/ Information Engineering/ IC Design or related fields with 6+ years’ experience, or Master’s Degree with 3+ years’ experience, or PhD holder in related area. Candidates with less experience will be considered as Engineer.
  • Experience in HDL coding (Verilog, VHDL) is preferred.
  • Hands-on experience in IC design and verification (e.g. System Verilog) is preferred.
  • Experience in FPGA prototyping and debugging is an advantage.
  • Algorithm Design experience in Matlab/C in Digital Communications or Cryptography is an advantage.
  • Excellent analytical and troubleshooting skills.
  • Fast learner and able to work independently.
  • Passionate about new technology.
  • Proficiency in electronic and circuit would be an advantage.


Appointment will be on renewable contract terms with a competitive salary and performance-linked variable pay. Fringe benefits include paid leave, medical and dental benefits, insurance coverage and contribution to MPF. The incumbent will normally work under a five-day week schedule.

Interested candidates should send application (quoting Ref. No.) with detailed resume and, current and expected salary to the HR Department by email. Application open until this position is filled.


Post: 5/F, Photonics Centre, 2 Science Park East Avenue,

Hong Kong Science Park, Shatin, Hong Kong.

Only short-listed candidates will be notified. Personal data provided by applicants will be used for consideration of an application only. ASTRI reserves the right not to fill the position.